Creating thin films having a large capacitance density, that is, a capacitance density above about 1 μF/cm2 on metal sheets presents a number of challenges. One way to achieve large capacitance density would be to achieve a large dielectric constant, given that capacitance density and dielectric constant are directly proportional to one another. It is well known that the dielectric constant of a material is among other things a function of the grain size of that material. In particular, as the grain size of a material increases, generally, so will its dielectric constant. However, growing thin films having large grain sizes, that is, thin films having grain sizes above about 50 nm to about 100 nm is a challenge. For example, growing a large grain microstructure requires an optimum combination of nucleation and grain growth. This is hard to achieve on a polycrystalline metal sheet. Typically, the multitude of random sites on the rough polycrystalline metal sheet acts as nucleation sites, resulting in a microstructure with very small grain size (about 10 nm to about 50 nm). Once the film microstructure is composed of a large number of small grains, further heating will not result in a large grain microstructure, because larger grains would grow at the expense of the smaller grains. However, a large number of similar-sized grains cannot grow into each other to form larger grains.
As a result of the above, attempts at creating thin films having a large capacitance density has shifted toward reducing a thickness of the deposited thin film dielectric, while avoiding the problems noted above with respect to creating dielectrics of large grain size. Thus, the prior art typically focuses on small grain sized thin film technology (that is dielectric thin films having grain sizes in the range from about 10 nm to about 50 nm, with dielectric constants ranging from about 100 to about 450. To the extent that the capacitance density of a material is known to be inversely proportional to its thickness, the prior art has aimed at keeping the thickness of such dielectric films in the order of about 0.1 microns. However, disadvantageously, such films have tended to present serious shorting issues. First, a surface roughness of the metal sheet onto which the dielectric film has been deposited, to the extent that it is usually significant with respect to a thickness of the dielectric film, tends to present metal peak and valleys into the dielectric film which in turn can lead to a direct shorting between the electrodes of a capacitor that includes the dielectric film. In addition, again, since a thickness of the dielectric film is small, voids typically present in the film will allow metal from at least one of the capacitor electrodes to seep into the voids, leading to shorting and leakage between the electrodes.
Voids in dielectric layers are disadvantageous for a number of other reasons. First, because of the presence of air pockets brought about as a result of the presence of voids, stress concentration points are typically created in the dielectric film, thus increasing the risk of crack propagation therein. In addition, to the extent that the dielectric constant of air is very small, the presence of air pockets results in an overall decrease in the dielectric constant of the dielectric layer. Thus, voids present disadvantages with respect to both the mechanical integrity and the electrical performance of a dielectric layer. The prior art proposes solving the problem of voids by exposing the dielectric layer to relatively long periods of sintering in order to densify the layer. However, such a solution disadvantageously increases the thermal budget required for the fabrication of a dielectric film, increasing cost while not necessarily guaranteeing a satisfactory reduction in the number of voids.
With respect to fabricating thin film capacitors, as noted above, a predominant prior art method involves chemical solution deposition (CSD). Referring to FIGS. 1A–1F, various stages of a prior art CSD method for creating a dielectric thin film are depicted. As seen in FIG. 1A, the shown CSD method involves the deposition of a CSD precursor film 10 onto a metal sheet or electrode 12. Deposition of the precursor may be achieved using well known spin-on deposition, spraying and dipping techniques. Thereafter, at FIG. 1B, the deposited precursor film 10 is shown as having been subjected to drying, burn-out of organics and annealing through heat treatment. As seen in FIG. 1B, heat treatment results in the decomposition of residual organics in the precursor and further in the growth of small-sized grains, which together contribute to form a first layer 14 of dielectric material. In FIGS. 1C and 1D, and in FIGS. 1E and 1F, fabrication stages similar to those in FIGS. 1A and 1B are respectively depicted. Thus, the deposition of a precursor film 10′ and 10″ as seen in FIGS. 1C and 1E is followed by heat treatment as seen in FIGS. 1D and 1F to yield second and third layers 14′ and 14″ of dielectric material, respectively. The resulting dielectric film 16 as shown in FIG. 1F disadvantageously contains grains of small size, in the order of about 10 nm to about 50 nm, thus exhibiting a low effective dielectric constant, typically in the range from about 100 to about 450. In addition, voids present in the dielectric film 16 tend to create shorts between the two electrodes of a capacitor formed from assembly 18 of FIG. 1F, as explained above.
Conventional thin film dielectric fabrication methods thus do not allow the formation of a dielectric film that both exhibits a high capacitance density and substantially avoids shorting and/or leakage issues between electrodes in a capacitor including the film.